module branch (branch,rs,j,jump);

    input   [2:0]   branch;
    input   [15:0]  rs;
    input           j;
    output          jump;

    wire    rs_is_zero,rs_is_neg;
    assign  rs_is_zero = ~(| rs);
    assign  rs_is_neg = rs[15];

    assign   jump = (j==1'b1)?1'b1
                :   (branch[2]==1'b0)?1'b0
                :   (branch[1]==1'b0)?
                        ((branch[0]==1'b0)?rs_is_zero:~rs_is_zero)
                    :   ((branch[0]==1'b0)?rs_is_neg:~rs_is_neg)
                    ;
                    
endmodule
